《数字电子技术（第十版）（英文版）》是2011年10月电子工业出版社出版的图书，作者是余璆。
本书是一本关于数字电子技术的经典教材，并专门针对国内教学的实际情况进行了缩减。全书主要介绍了数字电子技术的基本概念、数制、逻辑门、布尔代数和逻辑化简、组合逻辑分析、组合逻辑的作用、计数器、移位寄存器、存储器、可编程逻辑与软件、集成电路技术等。全书的特色在于示例与习题丰富、图解清晰、语言流畅、写作风格简约。
目录
- CONTENTS
- Chapter 1 Introductory Concepts 1
- 1–1 Digital and Analog Quantities 1
- 1–2 Binary Digits, Logic Levels, and Digital Waveforms 3
- 1–3 Fixed-Function Integrated Circuits 8
- Chapter 2 Number Systems, Operations, and Codes 16
- 2–1 Decimal Numbers 16
- 2–2 Binary Numbers 17
- 2–3 Decimal-to-Binary Conversion 20
- 2–4 Binary Arithmetic 22
- 2–5 1’s and 2’s Complements of Binary Numbers 26
- 2–6 Signed Numbers 27
- 2–7 Arithmetic Operations with Signed Numbers 33
- 2–8 Hexadecimal Numbers 39
- 2–9 Octal Numbers 45
- 2–10 Binary Coded Decimal (BCD) 47
- 2–11 Digital Codes 50
- 2–12 Error Detection Codes 52
- Chapter 3 Logic Gates 66
- 3–1 The Inverter 66
- 3–2 The AND Gate 68
- 3–3 The OR Gate 75
- 3–4 The NAND Gate 79
- 3–5 The NOR Gate 83
- 3–6 The Exclusive-OR and Exclusive-NOR Gates 87
- 3–7 Fixed-Function Logic 90
- Chapter 4 Boolean Algebra and Logic Simplification 110
- 4–1 Boolean Operations and Expressions 110
- 4–2 Laws and Rules of Boolean Algebra 111
- 4–3 DeMorgan’s Theorems 116
- 4–4 Boolean Analysis of Logic Circuits 119
- 4–5 Simplification Using Boolean Algebra 122
- 4–6 Standard Forms of Boolean Expressions 125
- 4–7 Boolean Expressions and Truth Tables 131
- 4–8 The Karnaugh Map 135
- 4–9 Karnaugh Map SOP Minimization 137
- 4–10 Five-Variable Karnaugh Maps 147
- System Application Activity 149
- Chapter 5 Combinational Logic Analysis 163
- 5–1 Basic Combinational Logic Circuits 163
- 5–2 Implementing Combinational Logic 168
- 5–3 The Universal Property of NAND and NOR Gates 173
- 5–4 Combinational Logic Using NAND and NOR Gates 175
- 5–5 Logic Circuit Operation with Pulse Waveform Inputs 180
- System Application Activity 183
- Chapter 6 Functions of Combinational Logic 197
- 6–1 Basic Adders 197
- 6–2 Parallel Binary Adders 200
- 6–3 Ripple Carry Versus took-Ahead Adders 206
- 6–4 Comparators 210
- 6–5 Decoders 213
- 6–6 Encoders 221
- 6–7 Code Converters 225
- 6–8 Multiplexers (Data Selectors) 228
- 6–9 Demultiplexers 236
- 6–10 Parity Generators/Checkers 237
- System Application Activity 240
- Chapter 7 Latches, Flip-Flops, and Timers 260
- 7–1 Latches 260
- 7–2 Edge-Triggered Flip-Flops 266
- 7–3 Flip-Flops Operating Characteristics 277
- 7–4 Flip-Flops Applications 279
- 7–5 One-Shots 283
- 7–6 The Astable Multivibrator 291
- System Application Activity 294
- Chapter 8 Counters 308
- 8–1 Asynchronous Counters 308
- 8–2 Synchronous Counters 316
- 8–3 Up/Down Synchronous Counters 322
- 8–4 Design of Synchronous Counters 326
- 8–5 Cascaded Counters 335
- 8–6 Counter Decoding 338
- 8–7 Counter Applications 342
- 8–8 Logic Symbols with Dependency Notation 346
- System Application Activity 348
- Chapter 9 Shift Registers 363
- 9–1 Basic Shift Register Operations 363
- 9–2 Serial In/Serial Out Shift Registers 364
- 9–3 Serial In/Parallel Out Shift Registers 368
- 9–4 Parallel In/Serial Out Shift Registers 370
- 9–5 Parallel In/Parallel Out Shift Registers 374
- 9–6 Bidirectional Shift Registers 375
- 9–7 Shift Register Counters 378
- 9–8 Shift Register Applications 381
- 9–9 Logic Symbols with Dependency Notation 389
- System Application Activity 390
- Chapter 10 Memory and Storage 402
- 10–1 Memory Basics 402
- 10–2 The Random-Access Memory (RAM) 406
- 10–3 The Read-Only Memory (RAM) 419
- 10–4 Programmable ROMs 423
- 10–5 The Flash Memory 426
- 10–6 Memory Expamsion 430
- 10–7 Special Types of Memories 436
- 10–8 Magnetic and Optical Storage 441
- System Application Activity 447
- Chapter 11 Signal Interfacing and Processing 458
- 11–1 Converting Analog Signals to Ditital 458
- 11–2 Analog-to-Digital Conversion Methods 464
- 11–3 Digital-to-Analog Conversion Methods 475
- 11–4 Digital Signal Processing Basics 483
- Chapter 12 Integrated Circuit Technologies 491
- 12–1 Basic Operational Characteristics and Parameters 491
- 12–2 CMOS Circuits 498
- 12–3 TTL (Bipolar) Circuits 503
- 12–4 Practical Considerations in the Use of TTL. 508
- 12–5 Comparison of CMOS and TTL Performance 515
- 12–6 Emitter-Coupled Logic (ECL) Circuits 516
- 12–7 PMOS, NMOS, and E2CMOS 518
- Appendix A Karnaugh Map POS Minimization 529
- Appendix B The Quine-McCluskey Method 533
- Appendix C NI Multisim for Circuit Simulation 536
- Answers to Odd-Numbered Problems 541
